关于发动代码2440init.s（三）

;=======================================================================
; 哈哈,下面又有看头了,这个初始化程序好像被名曰hzh的高手改正
; 能在NOR NAND 还有内存中运转,当然了,在内存中运转最简略了.
; 在NOR NAND中运转的话都要先把自己拷到内存中.
; 此外,还记得上面说到的|Image$$RO$$Base|,|Image$$RO$$Limit|…吗?
; 这便是仿制的依据了!!!
;=========================================================================

;BWSCON的[2:1]反映了外部引脚OM[1:0]:若OM[1:0] != 00, 从NOR FLash发动或直接在内存运转；若OM[1:0]==00，则为Nand Flash Mode
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ; #6 == 0110 –> BWSCON[2:1]
bne copy_proc_beg ;OM[1:0] != 00，NOR FLash boot，不读取NAND FLASH

adr r0, ResetEntry ;不然,OM[1:0] == 0, 为从NAND FLash发动
cmp r0, #0 ;再比较进口是否为0地址处
;假如是0才是真正从NAND 发动，由于其4k被仿制到0地址开端的stepingstone 内部sram中
; 留意adr得到的是 相对 地址，非肯定地址 == if use Multi-ice,
bne copy_proc_beg ;假如!=0,阐明在using ice, 这种状况也不读取NAND FLASH. dont read nand flash for boot
;nop

;==============这一段代码完结从NAND Flash读代码到RAM=====================
nand_boot_beg ;
mov r5, #NFCONF ;首要设定NAND的一些操控寄存器
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID ;按着读取NAND的ID号,成果保存在r5里
mov r6, #0 ;r6设初值0.
ldr r0, =0xec73 ;希望的NAND ID号
cmp r5, r0 ;这儿进行比较
beq � ;持平的话就跳到下一个1标号处
ldr r0, =0xec75 ;这是另一个希望值
cmp r5, r0
beq � ;持平的话就跳到下一个1标号处
mov r6, #1 ;不持平,设置r6=1.
1
bl ReadNandStatus ;读取NAND状况,成果放在r1里
mov r8, #0 ; r8设初值0,含义为页号
ldr r9, =ResetEntry ; r9设初值为初始化程序进口地址
; 留意,在这儿运用的是ldr伪指令,而不是上面用的adr伪指令,它加载的是ResetEntry
; 的肯定地址,也便是咱们希望的RAM中的地址,在这儿,它和|Image$$RO$$Base|相同
; 也便是说,我如咱们编译程序时RO base指定的地址在RAM里,而把生成的文件拷到
; NAND里运转,由ldr加载的r9的值仍是定位在内存. ???

2
ands r0, r8, #0x1f ;凡r8为0x1f(32)的整数倍-1,eq有用,ne无效
bne � ;这句的意思是对每个块(32页)进行检错 — 在每个块的开端页进行
mov r0, r8 ;r8->r0
bl CheckBadBlk ;查看NAND的坏区
cmp r0, #0 ;比较r0和0
addne r8, r8, #32 ;存在坏块的话就越过这个坏块: + 32得到下一块. 故: r8 = blockpage addr，由于读写是按页进行的(每页512Byte)
bne � ;然后跳到4进行循环条件判别。没有的话就跳到标号3处copy当时页
3
mov r0, r8 ;当时页号->r0
mov r1, r9 ;当时方针地址->r1
bl ReadNandPage ;读取该页的NAND数据到RAM
add r9, r9, #512 ;每一页的巨细是512Bytes
add r8, r8, #1 ;r8指向下一页
4
cmp r8, #256 ;比较是否读完256页即128KBytes
;留意：这阐明此程序默许仿制128KByte的代码(by Tinko)

bcc � ;假如r8小于256(没读完),就回来前面的标号2处
; now copy completed
mov r5, #NFCONF ;Disable NandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]

ldr pc, =copy_proc_beg ;调用copy_proc_beg
;个人认为应该为InitRam ?????????????????????????????



;===========================================================
copy_proc_beg
adrl r0, ResetEntry ;ResetEntry值->r0
;这儿应该留意，运用的是adr，而不是ldr。运用ldr阐明ResetEntry是个肯定地址，这个地址是在程序链接的时分
;确认的。而运用adr则阐明ResetEntry的地址和当时代码的履行方位有关，它是一个相对的地址。比方这段代码
;在stepingstone里边履行，那么ResetEntry的地址便是零。假如在RAM里履行，那么ResetEntry就应是ＲＡＭ的一个
;地址，应该等于RO base。
ldr r2, BaseOfROM ;BaseOfROM值(后边有界说)->r2
cmp r0, r2 ;比较 ResetEntry 和 BaseOfROM
ldreq r0, TopOfROM ;假如持平的话(在内存运转 — ice — 无需仿制code区中的ro段，但需求仿制code区中的rw段),TopOfROM->r0
beq InitRam ;一起跳到InitRam
;不然，下面开端仿制code的RO段
;=========================================================
;下面这个是针对代码在NOR FLASH时的仿制办法
;功能为把从ResetEntry起,TopOfROM-BaseOfROM巨细的数据拷到BaseOfROM
;TopOfROM和BaseOfROM为|Image$$RO$$Limit|和|Image$$RO$$Base|
;|Image$$RO$$Limit|和|Image$$RO$$Base|由连接器生成
;为生成的代码的代码段运转时的起启和停止地址
;BaseOfBSS和BaseOfZero为|Image$$RW$$Base|和|Image$$ZI$$Base|
;|Image$$RW$$Base|和|Image$$ZI$$Base|也是由连接器生成
;两者之间便是初始化数据的寄存地
; –在加载阶段，不存在ZI区域–
;=======================================================
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7} ;开端时，r0 = ResetEntry — source
stmia r2!, {r4-r7} ;开端时，r2 = BaseOfROM — destination
cmp r2, r3 ;停止条件：仿制了TopOfROM-BaseOfROM巨细
bcc �

;—————————————————————
; 下面2行，依据了解，由tinko增加
; 猜想上面的代码不该该用” ! “，以至于地址被修正。这儿从头赋值
;—————————————————————
adrl r0, ResetEntry ;dont use adr, cause out of range error occures
ldr r2, BaseOfROM
;旨在核算出正确的RW区开端方位
; 下面2行意图是为了核算正确的r0（有必要使之指向code区中的rw域开端处）
sub r2, r2, r3 ;r2=BaseOfROM-TopOfROM=(-)代码长度
sub r0, r0, r2 ;r0=ResetEntry-(-)代码长度=ResetEntry+代码长度

InitRam
;仿制代码加载方位中的RM区到|Image$$RW$$Base|
ldr r2, BaseOfBSS ;BaseOfBSS->r2 , BaseOfBSS = |Image$$RW$$Base|
ldr r3, BaseOfZero ;BaseOfZero->r3 , BaseOfZero = |Image$$ZI$$Base|
0
cmp r2, r3 ;比较BaseOfBSS和BaseOfZero
ldrcc r1, [r0], #4 ;当代码在内存中运转时，r0(初始值) = TopOfROM.这之后的BaseOfZero-BaseOfBSS仍归于code，需仿制到BaseOfBSS
strcc r1, [r2], #4
bcc �

;用0初始化ZI区
mov r0, #0
ldr r3, EndOfBSS ;EndOfBSS = |Image$$ZI$$Limit|
1
cmp r2, r3
strcc r0, [r2], #4
bcc �

;要是r21 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;===========================================================

; 进入C言语前的最终一步了,便是把咱们用说查二级向量表
; 的中止例程安装到一级向量表(反常向量表)里.
;//5.设置缺省中止处理函数
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there isnt subs pc,lr,#4 at 0x18, 0x1c
str r1,[r0]
;//initialize the IRQ 将一般中止判别程序的进口地址给HandleIRQ

;//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
;留意，以下这段或许不需求!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;//6.将数据段仿制到ram中 将零初始化数据段清零跳入C言语的main函数履行到这步完毕bootloader开始引导完毕
;If main() is used, the variable initialization will be done in __main().
[ {FALSE} ;by tinko — 最外面的条件由tinko增加，实际上不再履行这段
[ :LNOT:USE_MAIN ;initialized {FALSE}
;Copy and paste RW data/zero initialized data

LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|

;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different just for debug??????????????????????????
BEQ �
1
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;–> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;–> STRCC r2, [r1] + ADD r1, r1, #4
BCC �
2
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
3
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC �
]
]
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

;***************************************
;by tinko
[ {TRUE} ;得有些表明了,该点点LED灯了
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0xe0
str r1,[r0]

ldr r2, =0xffffffff;
1
sub r2,r2,#1
bne �
ldr r0,=GPFDAT
ldr r1,=0xe0
;b . ;die here
]
;*****************************************
;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
; 妈呀,终说见到艳阳天了!!!!!!!!!!
; 跳到C言语的main函数处了.
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************

[ :LNOT:THUMBCODE ;if thumbcode={false} bl main L代表logic变量
bl Main ;Dont use main() because ……
b . ;留意小圆点
]

;//if thumbcod={ture}
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Dont use main() because ……
b . ;留意小圆点
CODE32
]

;function initializing stacks
InitStacks
;Dont use DRAM,such as stmfd,ldmfd……
;SVCstack is initialized before
;Under toolkit ver 2.5, msr cpsr,r1 can be used instead of msr cpsr_cxsf,r1

mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;//为什么不必初始化user的stacks，体系刚发动的时分运转在哪个形式下？
mov pc,lr
;The LR register wont be valid if the current mode is not SVC mode.？
;//体系一开端运转便是SVCmode？
;===========================================================
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq �
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq �
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne �
2
ldr r0, [r5, #0x20]
tst r0, #1
beq �
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc �
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]

mov pc,r7
;——————–LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne �
mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne �
b �
mov pc, lr
;===========================================================
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144

CLKDIV124

ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 – 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr

;存储器操控寄存器的界说区
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+ (B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+ (B6_BWSCON<<24)+(B7_BWSCON<<28)) ;各bank的bus width; 没有B0，由于由 OM[1:0]pins 确认
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 B6_MT界说在memcfg.inc中，11–>SDRAM ; B6_SCAN – 非reset 默许值
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;Tchr- not used
;DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x31 ;SCLK power saving mode, BANKSIZE 64M/64M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|

ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Dont use the label IntVectorTable,
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
; 2003.03.14:DonGo: Modified for 2440.
; 2009 06.24:Tinko Modified