FPGA verilog完成的1602时钟计数器

原文链接：熬夜到了1点了，总算写出了1602的时钟计数器代码。为什么是时钟计数器呢？由于我还没来得及做校准时刻，所以只能称之为时钟计数器，不能成为电子钟。网上很少用人揭露这一类代码，一搜FPGA 1602，都是写一个静态的显现，在实践使用中，是没有用的，因而这个简略的比如，给我们抛砖引玉了！上代码： Qii 9.0编译过，21EDA 开发板测验OKmodule LCD(rst,key1,clk,rw,rs,en,data);input clk,rst,key1;output rs,en,rw;output [7:0] data;reg rs,en_sel;reg [7:0] data;reg [7:0] shi,fen,miao;reg [31:0]count,count1;//LCD CLK 分频计数器reg lcd_clk;reg [7:0] one_1,one_2,one_3,one_4,one_5,one_6,one_7,one_8,one_9,one_10,one_11,one_12,one_13,one_14,one_15,one_16;reg [7:0] two_1,two_2,two_3,two_4,two_5,two_6,two_7,two_8,two_9,two_10,two_11,two_12,two_13,two_14,two_15,two_16;reg [7:0] next,xianshi,two;parameterstate0 =8h00, //设置8位格局,2行,5*7 8h38;state1 =8h01,//全体显现,关光标,不闪耀 8h0C 闪耀 8h0estate2 =8h02,//设定输入方法,增量不移位8h06state3 =8h03,//铲除显现8h01state4 =8h04,//显现榜首行的指令80Hstate5 =8h05,//显现第二行的指令80H+40Hscan=8h06,nul=8h07;parameterdata0 =8h10, //2行，共32个数据data1 =8h11,data2 =8h12,data3 =8h13,data4 =8h14,data5 =8h15,data6 =8h16,data7 =8h17,data8 =8h18,data9 =8h19,data10 =8h20,data11 =8h21,data12 =8h22,data13 =8h23,data14 =8h24,data15 =8h25,data16 =8h26,data17=8h27,data18=8h28,data19=8h29,data20=8h30,data21 =8h31,data22 =8h32,data23 =8h33,data24 =8h34,data25 =8h35,data26 =8h36,data27 =8h37,data28 =8h38,data29 =8h39,data30 =8h40,data31 =8h41;iniTIal //初始值begin//榜首行显现TEL:13868160569one_1=T; one_2=E; one_3=L; one_4=:; one_5=1; one_6=3; one_7=8; one_8=6;one_9=8;one_10=1;one_11=6;one_12=0;one_13=5;one_14=6;one_15=9;one_16= ;//第二行显现 Clock：00-00-00two_1=C; two_2=l; two_3=o; two_4=c; two_5=k; two_6=:; two_7= ; two_8= ;two_9=-;two_10= ;two_11= ;two_12=-;two_13= ;two_14= ;two_15= ;two_16= ;shi=0;fen=0;miao=0;endalways @(posedge clk )//取得LCD时钟begincount=count+1;if(count==250000)begincount=0;lcd_clk=~lcd_clk;endendalways @(posedge clk or negedge rst)//时钟计数器beginif(!rst)beginshi=0;fen=0;miao=0;count1=0;endelsebeginen_sel=1;two_7=(shi/10)+8b00110000;two_8=(shi%10)+8b00110000;two_10=(fen/10)+8b00110000;two_11=(fen%10)+8b00110000;two_13=(miao/10)+8b00110000;two_14=(miao%10)+8b00110000;count1=count1+1b1;if(count1==49999999) // 时钟计数begincount1=0;miao=miao+1;if(miao==59)beginmiao=0;fen=fen+1;if(fen==59)beginfen=0;shi=shi+1;if(shi==23)beginshi=0;endendendendendendalways @(posedge lcd_clk )begincase(next)state0 :begin rs=0; data=8h38; next=state1; end //装备液晶state1 :begin rs=0; data=8h0e; next=state2; endstate2 :begin rs=0; data=8h06; next=state3; endstate3 :begin rs=0; data=8h01; next=state4; endstate4 :begin rs=0; data=8h80; next=data0; end//显现榜首行data0 :begin rs=1; data=one_1; next=data1 ; enddata1 :begin rs=1; data=one_2; next=data2 ; enddata2 :begin rs=1; data=one_3; next=data3 ; enddata3 :begin rs=1; data=one_4; next=data4 ; enddata4 :begin rs=1; data=one_5; next=data5 ; enddata5 :begin rs=1; data=one_6; next=data6 ; enddata6 :begin rs=1; data=one_7; next=data7 ; enddata7 :begin rs=1; data=one_8; next=data8 ; enddata8 :begin rs=1; data=one_9; next=data9 ; enddata9 :begin rs=1; data=one_10; next=data10 ; enddata10 :begin rs=1; data=one_11; next=data11 ; enddata11 :begin rs=1; data=one_12; next=data12 ; enddata12 :begin rs=1; data=one_13; next=data13 ; enddata13 :begin rs=1; data=one_14; next=data14 ; enddata14 :begin rs=1; data=one_15; next=data15 ; enddata15 :begin rs=1; data=one_16; next=state5 ; endstate5:begin rs=0;data=8hC0; next=data16; end //显现第二行data16 :begin rs=1; data=two_1; next=data17 ; enddata17 :begin rs=1; data=two_2; next=data18 ; enddata18 :begin rs=1; data=two_3; next=data19 ; enddata19 :begin rs=1; data=two_4; next=data20 ; enddata20 :begin rs=1; data=two_5; next=data21 ; enddata21 :begin rs=1; data=two_6; next=data22 ; enddata22 :begin rs=1; data=two_7; next=data23 ; enddata23 :begin rs=1; data=two_8; next=data24 ; enddata24 :begin rs=1; data=two_9; next=data25 ; enddata25 :begin rs=1; data=two_10; next=data26 ; enddata26 :begin rs=1; data=two_11; next=data27 ; enddata27 :begin rs=1; data=two_12; next=data28 ; enddata28 :begin rs=1; data=two_13; next=data29 ; enddata29 :begin rs=1; data=two_14; next=data30 ; enddata30 :begin rs=1; data=two_15; next=data31 ; enddata31 :begin rs=1; data=two_16; next=scan ; endscan://替换更新榜首行和第二行数据beginnext=state4;enddefault: next=state0;endcaseendassign en=lcd_clk en_sel;assign rw=0;endmodule