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PIC 、APIC(IOAPIC LAPIC)

1OverviewPIC全称ProgrammableInterruptController,通常是指Intel8259A双片级联构成的最多支持15个interrupts的中断控制系统。AP

1. Overview

PIC全称Programmable Interrupt Controller,一般是指Intel 8259A双片级联构成的最多支撑15个interrupts的中止控制体系。APIC全称Advanced Programmable Interrupt Controller,APIC是为了多核渠道而规划的。它由两个部分组成IOAPICLAPIC,其间IOAPIC一般坐落南桥中用于处理桥上的设备所发生的各种中止,LAPIC则是每个CPU都会有一个。IOAPIC经过APICBUS(现在都是经过FSB/QPI)将中止信息分派给每颗CPU的LAPIC,CPU上的LAPIC可以智能的决议是否承受体系总线上传递过来的中止信息,并且它还可以处理Local端中止的pending、nesting、masking,以及IOAPIC于Local CPU的交互处理。

2. PIC

依据Intel 80×86的PC运用两片8259A级联的方法组成了可以办理15级中止向量的一个中止体系,下图是它的一个衔接示意图。两片8259A,一片为Master,另一片为Slaver。其间Slaver的INT接到Master的IRQ2上。8259A有两种作业形式分别为编程和操作形式。BIOS初始化的时分会先经过IO port对8259A进行编程装备,在此之后8259A就可以呼应来自外部设备的中止请求了。Master的IO address是0x20 0x21; Slaver的IO address是0xA0 0xA1。

为了可以正常的运用PIC来办理体系中止,就需要对它进行初始化。8259A支撑两种类型的命令字,一类是初始化命令字ICW1~4,另一类是操作命令字OCW1~3,其间每一个命令字的各个bit都有其代表的特定含义。下述是一个初始化Master的一个sample code:

MOVAL,00010001b;级联,边缘触发,需要写ICW4

OUT20H,AL;写ICW1

MOVAL,01000000B ;中止类类型40H

OUT21H,AL;写ICW2

MOVAL,00000100B;主片的IR2引脚从片

OUT21H,AL;写ICW3

MOVAL,00010001B;特别彻底嵌套,非缓冲,主动完毕

OUT21H,AL;写ICW4

3. APIC

Intel APIC由一组中止输入信号,一个24*64bit的Programmable Redirection Table(PRT),一组register和用于从APIC BUS(FSB/QPI)上传送APIC MSG的部件组成,当南桥的IO device经过IOAPIC的interrupt lines发生interrupt,IOAPIC将依据内部的PRT table格局化成中止请求信息,并将该信息发送给方针CPU的LAPIC,再由LAPIC告诉CPU进行处理。下图是一个依据Intel APIC的衔接示意图,如下图所示IOAPIC上有24个interrupt pin,每一个pin都对应一个RTE,所以针对每一个interrupt pin都可以独自设定它的mask,触发方法(level,edge trigger),中止管脚的极性,传送方法,传送状况,目的地,中止向量等。

Programmable Redirection Table具体格局如下所示:

Bit Description:

[63:56] Destination Field—R/W.If the Destination Mode of this entry is Physical Mode (bit 11=0), bits

[59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field

potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical

destination address.

Destination Mode IOREDTBLx[11] Logical Destination Address

0, Physical Mode IOREDTBLx[59:56] = APIC ID

1, Logical Mode IOREDTBLx[63:56] = Set of processors

[55:17] Reserved.82093AA (IOAPIC)

[16]Interrupt Mask—R/W.When this bit is 1, the interrupt signal is masked. Edge-sensitive

interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending).

Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no

side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by

a local APIC has no effect on that interrupt. This behavior is identical to the case where the

device withdraws the interrupt before that interrupt is posted to the processor. It is softwares

responsibility to handle the case where the mask bit is set after the interrupt message has been

accepted by a local APIC unit but before the interrupt is dispensed to the processor. When this

bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked

results in the delivery of the interrupt to the destination.

[15] Trigger Mode—R/W.The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 1=Level sensitive, 0=Edge sensitive.

[14] Remote IRR—RO.This bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI message with a matching interrupt vector is received from a local APIC.

[13] Interrupt Input Pin Polarity (INTPOL)—R/W.This bit specifies the polarity of the interrupt

signal. 0=High active, 1=Low active.

[12]Delivery Status (DELIVS)—RO.The Delivery Status bit contains the current status of the

delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit

word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send

Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC

bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).

[11] Destination Mode (DESTMOD)—R/W.This field determines the interpretation of the

Destination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.

Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC.

Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC)

[10:8]Delivery Mode (DELMOD)—R/W.The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain

Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode.

These restrictions are indicated in the following table for each Delivery Mode.

Mode Description

000Fixed Deliver the signal on the INTR signal of all processor cores listed in the

destination. Trigger Mode for “fixed” Delivery Mode can be edge or level.

001Lowest

Priority Deliver the signal on the INTR signal of the processor core that is

executing at the lowest priority among all the processors listed in the

specified destination. Trigger Mode for “lowest priority”. Delivery Mode

can be edge or level.

010SMI System Management Interrupt. A delivery mode equal to SMI requires an

edge trigger mode. The vector information is ignored but must be

programmed to all zeroes for future compatibility.

011Reserved

100NMI Deliver the signal on the NMI signal of all processor cores listed in the

destination. Vector information is ignored. NMI is treated as an edge

triggered interrupt, even if it is programmed as a level triggered interrupt.

For proper operation, this redirection table entry must be programmed to

“edge” triggered interrupt.

101INIT Deliver the signal to all processor cores listed in the destination by

asserting the INIT signal. All addressed local APICs will assume their

INIT state. INIT is always treated as an edge triggered interrupt, even if

programmed otherwise. For proper operation, this redirection table entry

must be programmed to “edge” triggered interrupt.

110Reserved

111ExtINT Deliver the signal to the INTR signal of all processor cores listed in the

destination as an interrupt that originated in an externally connected

(8259A-compatible) interrupt controller. The INTA cycle that corresponds

to this ExtINT delivery is routed to the external controller that is expected

to supply the vector. A Delivery Mode of “ExtINT”requires an edge

trigger mode.

[7:0] Interrupt Vector (INTVEC)—R/W:The vector field is an 8 bit field containing the interrupt

vector for this interrupt. Vector values range from 10h to FEh.

REFF:

1.《82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAP%&&&&&%)》

2.《8259A PROGRAMMABLE INTERRUPT CONTROLLER(8259A/8259A-2)》

3.《Undocumented PC》

4.8259A初始化编程

That’s all!

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