最近在做Spartan6上的视频输出，输出的接口是HDMI接口，要求格局是720P。
体系的时钟首要有
1. 750M（TMDS输出的IO输出时钟，有必要接bufpll）
2. 75M（720P的像素时钟）
3. 150M
4. 100M （体系时钟）
5. 24M （外围设备需求的时钟）
东西是ISE12.2
然后经过ISE自带的Clock_wizard来生成需求的时钟，750M是专门用来做TMDS的IO输出时钟，首要端口界说如下：
–Clock_gen是经过Clock_wizard主动生成的。
Clock_gen_inst : clock_gen
port map(
CLK_IN1 => sys_clk_in,
RESET => sys_rst,
LOCKED => LOCKED,
CLK_OUT1 => pix_clkx10_pll, –750M, need bufpll as buffer
CLK_OUT2 => pix_clk_pll, –75M
CLK_OUT3 => pix_clkx2_pll, –150M
CLK_OUT4 => sys_clk， –93.75M
CLK_OUT5 => external_clk_buf );
而pix_clkx10_pll有必要增加bufpll
BUFPLL #(
.DIVIDE(5)
)
tx_bufpll_inst(
.IOCLK(tx_clkx10),
.LOCKED(LOCKED),
.LOCK(LOCK),
.PLLIN(pix_clkx10),
.GCLK(pix_clkx2),
.SERDESSTROBE(tx_serdesstrobe));
依照上面的时钟界说在mapping的时分呈现这样的error：
ROR:Place – ConstraintResolved NO placeable site for U2/tx_bufpll_inst
ERROR:Place – SIO has over-constrained componet U2/tx_bufpll_inst to have to placeable sites. Constraints come from
driver constraints AND load IO constraints
Phase 4.2 IniTIal Placement for Architecture Specific Features (Checksum:fc8413ca) REAL TIme: 38 secs
Total REAL TIme to Placer compleTIon: 38 secs
Total CPU time to Placer completion: 38 secs
ERROR:Pack:1654 – The timing-driven placement phase encountered an error.
Mapping completed.
See MAP report file hdmi_top_map.mrp for details.
Problem encountered during the packing phase.
经过增加PLL或许删去其间一个clock，测验了很屡次仍是报错。在网上找了，找到了相似的状况，可是没有给出解决方案来。
后来测验增加束缚才搞定的。直接指定bufpll的物理方位：
INST hdmi_encoder_0/hdmi_encoder_0/tx_bufpll_inst LOC= BUFPLL_X1Y5;
估量原因是：bufpll和OSERDES由于不在一个bank下导致无法进行mapping。见图1.
