SPC560P50L5 32位体系级芯片轿车使用计划

　　32-bit Power Architecture® based MCU with 1088KB Flash memory and 80KB RAM for automoTIve chassis and safety applicaTIons This 32-bit system-on-chip （SoC） automoTIve microcontroller family is the latest achievement in integrated automoTIve application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis applications specifically the airbag application.

　　This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology.

　　The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category. It operates up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers， operating systems and configuration code to assist with users implementations.

　　SPC560P50L5首要特性：

　　AEC-Q10x qualified 

　　64 MHz， single issue， 32-bit CPU core complex （e200z0h）

　　– Compliant with Power Architecture® embedded category

　　– Variable Length Encoding （VLE） 

　　Memory organization

　　– Up to 1024 KB on-chip code Flash memory with additional 64 KB for EEPROM emulation （data flash）， with ECC， with erase/program controller

　　– Up to 80 KB on-chip SRAM with ECC 

　　Fail safe protection

　　– ECC protection on system SRAM and Flash

　　– Safety port

　　– SWT with servicing sequence pseudo-random generator

　　– Power management

　　– Non-maskableinterrupt for both cores

　　– Fault collection and control unit （FCCU）

　　– Safe mode of system-on-chip （SoC）

　　– Register protection scheme 

　　Nexus® L2+ interface 

　　Single 3.3 V or 5 V supply for I/Os and ADC 

　　2 on-platform peripherals set with 2 INTC 

　　16-channel eDMA controller with multiple transfer request sources

　　General purpose I/Os （80 GPIO + 26 GPI on LQFP144; 49 GPIO + 16 GPI on LQFP100）  2 general purpose eTimer units

　　– 6 timers， each with up/down count capabilities

　　– 16-bit resolution， cascadable counters

　　– Quadrature decode with rotation direction flag

　　– Double buffer input capture and output compare 

　　Communications interfaces

　　– 2 LINFlex modules （LIN 2.1， 1 × Master/Slave， 1 × Master Only）

　　– 5 DSPI modules with automatic chip select generation

　　– 2 FlexCAN interfaces （2.0B Active） with 32 message buffers

　　– 1 Safety port based on FlexCAN; usable as third CAN when not used as safety port

　　– 1 FlexRay™ module （V2.1） with dual or single channel， 64 message buffers and up to 10 Mbit/s

　　2 CRC units with three contexts and 3 hardwired polynomials（CRC8，CRC32 and CRC-16-CCITT） 10-bit A/D converter

　　– 27 input channels and pre-sampling feature

　　– Conversion time 《 1 μs including sampling time at full precision

　　– Programmable cross triggering unit （CTU）

　　– 4 analog watchdog with interrupt capability 

　　On-chip CAN/UART Bootstrap loader with boot assist module （BAM） 

　　Ambient temperature ranges： –40 to 125℃ or –40 to 105℃

　　图1.SPC56xP54x/SPC56xP60x框图

　　SPC560P-DISP Discovery开发板

　　Discovery Kit for SPC56 P line – with SPC560P50L5 MCU　The SPC560P-DISP Discovery kit helps you to discover SPC56 P line Power Architecture® Microcontrollers. The discovery board is based on SPC560P50L5， 64 MHz， single issue， 32-bit CPU core complex （e200z0h） CPU core with 574KB flash in an LQFP144 package. The numerous interfaces including GPI/O ’s， peripherals such as CAN， JTAG， K-Line， LIN， FlexCAN and GPIOs make the SPC560P-DISP an excellent starter kit for customer quick evaluation and project development. Dedicated connectors allow plugging Arduino shields （Arduino-compatible）。 The SPC560 P line is designed to address cost sensitive chassis， airbag， electrical hydraulic power steering （EHPS）， electric power steering （EPS）， and electrical motor control applications.

　　SPC560P-DISP Discovery开发板首要特性：

　　• SPC560P50L5 32-bit 64MHz e200z0h CPU;32-bit Power Architecture® Technology CPU， 576 KB Flash in an LQFP144 package.

　　• Shield Connectors （Arduino compatible）。

　　• On-board USB-JTAG PLS debugger and HW selection mode to use stand-alone JTAG debuggers （2 x 7 male 100mil connector）。

　　• Free 128 Kbyte code size limited debugging

　　• Board power supply： from the USB bus （5 V supply voltage） or through external +12 V PSU.

　　• All GPIOs and DSPI/USB signals accessible by a 4×37 100mil pin grid array allowing connection of an additional boards for dedicated applications.

　　• CAN， K-LINE， LIN， FlexRay interfaces.

　　• Main power switch.

　　• Reset push button.

　　• 2 potentiometers for ADC evaluation

　　• 12 MHz crystal.

　　• Board size 152 x 103 mm

　　图2. SPC560P-DISP Discovery+板外形图

　　图3. SPC560P-DISP Discovery+板硬件概述图

　　图4. SPC560P-DISP Discovery+板电路图（1）

　　图5. SPC560P-DISP Discovery+板电路图（2）

　　图6. SPC560P-DISP Discovery+板电路图（3）

　　图7. SPC560P-DISP Discovery+板电路图（4）

　　图8. SPC560P-DISP Discovery+板电路图（5）

　　图9. SPC560P-DISP Discovery+板电路图（6）

　　图10. SPC560P-DISP Discovery+板电路图（7）

　　SPC560P-DISP Discovery+板材料清单：

　　图11. SPC560P-DISP Discovery+板PCB设计图

　　概况请见：

　　https://www.st.com/content/ccc/resource/technical/document/user_manual/26/69

　　/b1/12/40/38/4a/66/DM00116132.pdf/files/DM00116132.pdf/jcr:content/translations/en.DM00116132.pdf

　　和https://www.st.com/content/ccc/resource/technical/layouts_and_diagrams

　　/board_manufacturing_specification/47/6b/e0/fd/d3/a5/48/43/SPC560P-DISP_Schematic%20Diagram.pdf/files/SPC560P-DISP_Schematic%20Diagram.pdf/jcr:content/translations/en.SPC560P-DISP_Schematic%20Diagram.pdf

　　以及https://www.st.com/content/ccc/resource/technical/layouts_and_diagrams

　　/board_manufacturing_specification/24/2b/83/2d/f7/0d/4e/90/SPC560P-DISP__BOM.pdf/files/SPC560P-DISP__BOM.pdf/jcr:content/translations/en.SPC560P-DISP__BOM.pdf

　　en.DM00116132.pdf

　　spc56ap60l5（1）.pdf

　　en.SPC560P-DISP_Schematic Diagram.pdf

　　en.SPC560P-DISP__BOM.pdf