4定论
网络编码从提出到现在已有十年，在这期间，网络编码的理论研讨和工程运用不断发展和成熟，根据网络编码的多信源组播体系是网络编码在硬件方面的完结。它突破了以往网络编码的运用研讨只停留在软件和虚拟网络，经过建立实践的组播通讯网络，并运用NetFPGA渠道使网络编码在硬件中得以完结。
文档的前面别离介绍了网络编码的基本概念和研讨动态、编解码战略和算法以及编码、转发、解码三个体系的具体设计方案，包含体系的软硬接口和软件的基本功用。因为体系中的网络编解码都是由硬件完结，软件的功用主要是操控和测验时运用，因而方案设计以硬件为主。
图4-1，图4-2和图4-3别离是编码、转发以及解码路由器三个体系的verilog代码树状图，除掉MAC层和core generator发生的代码，代码量有11,000行。附录给出了编码路由器和解码路由器中的要害代码。
图4-1 编码路由器代码树状图
图4-2 转发路由器代码树状图
图4-3 解码路由器代码树状图
附录
附1：编码路由器中心代码：编码模块: payload_router.v
/////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// Copyright(c) 2009, All rights reserved.
// Advanced Network technology Lab, Shenzhen graduated school of PKU
// Module: payload_router.v
// Project: nf2_coding.ise
// Time and Author: 2009-12-25 liyining
// Description:determine whether should carry out coding operation, and route
// the packets
/////////////////////////////////////////////////////////////////////////////
`define DLY 1
`timescale 1ns/1ns
module payload_router
#(parameter DATAWIDTH = 64,
parameter CTRLWIDTH = DATAWIDTH / 8 //bit-width parameter
)
(
//payload fifo 1 port
input [DATAWIDTH – 1:0] data_payloadfifo_router_1,
input [CTRLWIDTH – 1:0] ctrl_payloadfifo_router_1,
input empty_payloadfifo_router_1,
output reg rd_en_payloadfifo_router_1,
//payload fifo 2 port
input [DATAWIDTH – 1:0] data_payloadfifo_router_2,
input [CTRLWIDTH – 1:0] ctrl_payloadfifo_router_2,
input empty_payloadfifo_router_2,
output reg rd_en_payloadfifo_router_2,
//multiplier 1 port
input rdy_router_multiplier_1,
output reg [DATAWIDTH – 1:0] data_router_multiplier_1,
output reg first_dword_1, //flag to indicate the start of a pkt. only when it is the first double word of a pkt, should the random number be updated.
output reg val_router_multiplier_1,
//multiplier 2 port
input rdy_router_multiplier_2,
output reg [DATAWIDTH – 1:0] data_router_multiplier_2,
output reg first_dword_2, //flag to indicate the start of a pkt. only when it is the first double word of a pkt, should the random number be updated.
output reg val_router_multiplier_2,
//rand number generator port
output reg rand_num_en, //enable the random number generator
input rand_num_val,
//packing fifo port
input rdy_router_packingfifo,
input empty_packingfifo, // only when the whole last pkt is sent out, and the packing fifo is empty, then proceed the next pkt
output reg [DATAWIDTH + CTRLWIDTH:0] data_router_packingfifo, //an extra bit(MSB) to indicate whether it is a coded pkt
output reg val_router_packingfifo,
output reg [2:0] router_status, //send router_status to packing_fifo, indicate where to get data
//misc
input clk,
input rst_n
);
reg [DATAWIDTH – 1:0] data_temp1;
reg [CTRLWIDTH – 1:0] ctrl_temp1;
reg [DATAWIDTH – 1:0] data_temp2;
reg [CTRLWIDTH – 1:0] ctrl_temp2;
reg [1:0] counter_getdata; //counter for the read-FIFO-delay, 1 clock circle
parameter JUDGE = 3’b000;
parameter GET_DATA2 = 3’b001;
parameter SEND_DATA2 = 3’b010;
parameter GET_DATA1 = 3’b011;
parameter SEND_DATA1 = 3’b100;
parameter GET_BOTH = 3b101;
