PowerPC简介及编程
一.PowerPC芯片
PowerPC是前期Motorola和IBM联合为Apple的MAC机开发的CPU芯片,商标权一起归于IBM和Motorola,并成为他们的主导制品.IBM首要的PowerPC产品有PowerPC604s(深蓝内部的CPU), PowerPC750,PowerPCG3(1.1GHz).Motorola首要有MC和MPC系列.虽然他们产品不一样,但都选用PowerPC的内核.这些产品大都用在嵌入式体系中.
二. Motorola的MPC860简介(摘抄)
MPC860 PowerQUICC (Quad Integrated Communications Controller) 内部集成了微处理器和一些操控范畴的常用外围组件, 特别适用于通讯产品. 包含器材的适应性, 扩展才能和集成度等. MPC860 PowerQUICC集成了两个处理块. 一个处理块是嵌入的PowerPC核, 另一个是通讯处理模块( CPM, Communications Processor Module), 通讯处理模块支撑四个串行通讯操控器(SCC, Serial Communication Controller), 实际上它有八个串行通道: 四个SCC，两个串行办理操控器 (SMC, Serial Management Channels), 一个串行外围接口电路 ( SPI, Serial Peripheral Interface ) 和一个I2C( Inter-Integrated Circuit ) 接口. 因为CPM分管了嵌入式PowerPC核的外围工作任务, 这种双处理器体系结构功耗要低于传统的体系结构的处理器.
1.单出口, 嵌入式PowerPC核32比特版别(与PowerPC结构界说彻底兼容)32×32位通用寄存器(GPRs, General Purpose Registers)
4K数据Cache和4K指令Cache, 别离带有一个MMU.
存储办理单元(MMU)32-输入翻译后备缓冲器 ( TLBs )
32位数据,地址线
2.存储操控器(八个存储体)
单线存储模块无逢接口，静态随即存取存储器(RAM), EPROM, FLASH MEMORY或DRAM等。
DRAM 操控器可编程支撑绝大多数不同巨细和速度的存储器
不同码组长度32K至256M
3.四个16位定时器或两个32位定时器.
4.体系集成单元 ( SIU, Sytstem Intergration Unit ) 首要包含:
软件看门狗
中止定时器
PowerPC 时基和实时时钟 (RTC, Real Time Clock )
复位操控器
JTAG 1149.1 测验口
5.中止体系包含7根外部中止请求线, 12个具有中止才能的管脚, 16个内部中止源. 中止优先级可编程
6.通讯处理器模块(CPM)首要包含:
RISC 操控器
5 K字节双口RAM
16个串行DMA (SDMA) 通道
三个平行 I/O 寄存器
7.四个波特率独立的产生器, 能够衔接到恣意一个SCC和SMC, 并答应运转中改动. 支撑主动波特率
8.四个串行通讯操控器 (SCC) ,支撑以太网, HDLC/SDLC, HDLC 总线(用以完成依据HDLC的局域网)、AppleTalk, 7号信令体系, UART、BISYNC, 比特流通明传输, 依据帧的通明传输 (CRC可选), 支撑PPP (Point to Point Protocol)的异步HDLC等规范协议
9.两个串行办理操控器 (SMC), UART办法或通明传输, 含GCI(General Circuit Interface)操控器, 能够连到时分复用通道
10.一个串行外围接口电路( SPI ), 是MC68302 SCP的扩展, 支撑主从形式, 支撑同一总线上多主操作
11.一个I2C ( Inter-Integrated Circuit ) 接口,支撑主从形式, 支撑多主环境
12.单插座PCMCIA-异步终端适陪器(ATA)接口
单PCMCIA插座
八贮存或有用输入/输出(I/O)窗口
三内存映射
MPC860的内存资源(如寄存器等)映射在一个接连的16K Block存储区内,可经过SPR中的Internal Map Memory Register(IMMR)进行解析
对 Memory Registers 操作的几种办法
Indirectly Access Registers Via Memory———————–经过指定的I/O寄存器(I/O port)对一个寄存器操作,
如PCI部分I/O操作示例如下:
PCI地址I/O寄存器: PCICFGADR 0xEEC00000
PCI数据I/O寄存器: PCICFGDATA 0xEEC00004
详细操作办法:将所要读写的寄存器地址写入PCI地址I/O寄存器PCICFGADR,从PCI数据I/O寄存器PCICFGDATA读出数据,这个数据便是写入地址的寄存器的数据.
RegAddr = 0x80000000 | ((offset|BusDevFunc) 0xFFFFFFFC);
RegAddr寄存器地址, 0x80000000 PCI core Address, offset寄存器偏移量
/*
* 写RegAddr到PCI I/O地址寄存器PCICFGADR
*/
sysPciOutLong(PCICFGADR, RegAddr);
/*
* 从PCI I/O数据寄存器读RegAddr数据data
*/
data = (unsigned int)sysPciInByte(PCICFGDATA | (offset 0x3));
Directly Access Registers Via Memory————————-直接对寄存器操作
Indirectly Access Registers Via DCR—————————–同上,
Directly Access Regesters Via DCR——————————-同上,
四,PowerPC内核界说
双处理器结构既供给了程序运转的通用途理器,又供给了用于通讯用途的特别通讯处理器(CPM).
1.32位PowerPC结构特色
32个32位通用寄存器 ( GPRs )
寄存器支撑用户级指令集 (不包含浮点指令),包含integer exception register (XER ),condition register(CR),link register(LR),counter register ( CTR )
时刻加减及寄存器
办理级寄存器,与PowerPC界说兼容
Configuration—–Machine Status Register ( MSR )
Exception model—–Save/restore registers 0 and 1 (SRR0 and SRR1), DSI status register ( DSISR ), data address register ( DAR )
PowerPC 减量器
PowerPC 时基和 实时时钟（RTC）
2.地址映射
|
称号 |
内存物理地址 |
补白 |
| SDRAM | 0x00000000~0x7FFFFFFF | |
| PCI | 0x80000000~0xEF5FFFFF | |
|
Internal Peripherals |
0xEF600000~0xEFFFFFFF | |
| UART | ….. | |
| ….. | ….. | |
|
External Peripherals |
0xF0000000~0xFF7FFFFF | |
| NVRAM/RTC |
0xF0000000~0xF0001FFF |
(8K)下画线为片选 |
| Keybord/Mouse | 0xF0100000~0xF0100001 | 下画线为片选 |
| FPGA_INT_ST.. | 0xF0300000~0xF0300000 | 下画线为片选 |
| FPGA_INT_EN.. | 0xF0300001~0xF0300001 | 下画线为片选 |
|
Socket Flash |
0xFFF80000~0xFFFFFFFF | 512K |
|
SRAM |
0xFFF00000~0xFFF7FFFF | 512K(可经过Swich与Socket Flash 切换) |
3.中止优先级(Exception Priority)
| Priority | Exception Type | Cause |
| 1 | Development port | nonmaskable interrupt Signal from the development port |
| 2 | System reset | interrupt IRQ0 assertion |
| 3 | Instruction-related exceptions | Instruction processing |
| 4 | Peripheral breakpoint request or development port maskable interrupt | Breakpoint signal from any peripheral |
| 5 | External interrupt (masked if MSR[EE] = 0) | Signal from the interrupt controller |
| 6 | Decrementer interrupt(masked if MSR[EE] = 0) | Decrementer request |
4.中止向量表
中止向量表的开端地址取决于MSR[IP]的设置
MSR[IP]=0 Exceptions are vectored to the physical address 0x000n_nnnn
MSR[IP]=1 Exceptions are vectored to the physical address 0xFFFn_nnnn
| Offset | Exception | Description |
| 0x00000 | Reserved | |
| 0x00100 | System reset interrupt | |
| 0x00200 | Machine check interrupt | |
| 0x00300 | DSI | A DSI exception is never generated by hardware, but software may branch to this location because of an data TLB error or miss exception. |
| 0x00400 | ISI | An ISI exception is never generated by the hardware, but software may branch to this location because of an implementation-speciTc instruction TLB error exception. |
| 0x00500 | External Interrupt | |
| … | … | … |
这个表结合地址映射表可知体系复位的地址是 Socket Flash地址+体系复位偏移地址 = 0xFFF80000 + 0x0100 = 0xFFF80100,即体系通电后,跳到0xFFF80100的方位开端履行程序.
5.MPC860串口中止过程
MPC860集成了两个处理块,一个处理块是嵌入的PowerPC核，另一个是通讯处理模块（CPM）.通讯处理模块有4个SCC和2个SMC,这六个通讯口能够经过设置来支撑多种协议和通讯办法,也可设置为串口UART形式(是经过寄存器GSMR或SMCMR),功用和中止的界说和一般的串口界说基本是共同的在寄存器SCCM/SCCE的位14和位15界说了在何种情况下产生硬件中止.
依据MPC860中SCC UART Event Register(SCCE)的位14和位15界说,位14是数据发送中止标志位,位15是数据接纳中止标志位,首要设置SCC UART Mask Register(SCCM)的位14和位15为1,使能承受和发送中止.
假如串口收到数据,则产生硬件RX中止,SCCE为15置1,告知体系有数据抵达,有相应的中止例程ISR来取数据.
发送的情况下,数据FIFO为空,产生TX中止,告知体系发送准备就绪,能够发送,ISR把数据放入FIFO中,发送中止位清零.当发送结束后,FIFO再为空,再次产生中止,告知体系发送准备就绪,持续发送.
6.MPC860片选信号的编程办法
在MPC860中，有片选信号CS0，CS1，…，CS7对他们的操作首要是要改动片选信号的电平.
一般来说片选信号的产生是对和这一片选线相关联的地址进行操作（读写）时片选信号改动。片选信号一般为低电平有用。比方MPC860的CS0是boot rom，硬件reset后，CPU会从boot rom的开端地址开端履行，CS0变为低电平。
所以只要对一个相应的地址操作，和这个地址芯片（bank)相连的CSx就会改动。
MPC860对CSx分配地址空间的在BRx中界说，BR0,BR1…BR7别离对应8个片选线CS0–CS7。
7.System Reset Interrupt (0x00100)
A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken, processing begins at offset 0x00100. A hard or soft reset also causes program execution to begin fetching at 0x00100 after the associated reset actions.
Register Setting
SRR0: Set to the (Effective Address) EA of the next instruction of the interrupted process.
SRR1: Saves the machine status prior to exceptions and to restore status when an r f i instruction is executed.
1-4 ,——-0
10-15,— 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR : IP No change ME No change LE Value of MSR[ILE] of the interrupted process. Others —–0
8.External Interrupt Exception (0x00500)
In the MPC860 the external interrupt is generated by the on-chip interrupt controller. It is software acknowledged and maskable by MSR[EE], which hardware clears automatically to disable external interrupts when any exception is taken.
Register Settings after an External Interrupt
Register Setting Description
SRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditions were present.
SRR1: 0, Loaded with equivalent bits from the MSR
1-4, Cleared; 5-9, Loaded with equivalent bits from the MSR; 10-15, Cleared; 16-31, Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR POW 0; ILE –; EE 0; PR 0; FP 0; ME –; SE 0; BE 0; IP –; IR 0; DR 0; RI 0; LE Set to value of ILE
9.Hard Reset ConTguration Word
The hard reset configuration word is sampled from the data bus. These bits determine the default values of the corresponding bits in the SIUMCR, IMMR, and MSR.
IIP:bit1: Initial interrupt prefix. Defines the initial value of the MSR[IP] which defines the interrupt table location. If
IIP is cleared (default), the MSR[IP] initial value is one; if it is set to one, the MSR[IP] initial value is zero.
ISB:bit 7-8, Initial internal space base select. Defines the initial value of the IMMR bits 0-15 and determines the
base address of the internal memory space.
00 0x00000000.
01 0x00F00000.
10 0xFF000000.
11 0xFFF00000.
